Field of the Invention
One disclosed aspect of the embodiments relates to an image processing apparatus for handling image data, a method for controlling the image processing apparatus, and a program therefor.
Description of the Related Art
Programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs) having internal programmable logical circuits are well known. In a PLD, logical circuit configuration information (hereinafter referred to as configuration data) stored in a read only memory (ROM) for configuration is written in a configuration memory which is an internal volatile memory. With this write operation, the operation of each logical block in the PLD is changed to configure a logical circuit. Writing configuration data in a PLD is referred to as configuration.
Recent PLDs are capable of performing partial reconfiguration of logical circuits. More specifically, changing the contents of the configuration data of a certain portion on the configuration memory enables changing only the operation of a logical block included in an area corresponding to the relevant certain portion out of all areas having a plurality of logical blocks included in the PLD. Japanese Patent Application Laid-Open No. 2011-186981 discusses a method for sequentially configuring a plurality of logical circuits configuring a pipeline in different areas in a PLD according to the progress of pipeline processing by using a partial reconfiguration technique.
The configuration data is stored in the ROM for configuration. When implementing a plurality of types of logical circuits, a plurality of types of configuration data is stored in this ROM, and differences between the plurality of types of configuration data stored in the ROM may be small.
In other words, since an identical portion of the configuration data is stored in the ROM in a duplicated way, the memory capacity required for storing the configuration data had increased.